TX CH1 interrupt raw register
| OUT_DONE_CH1_INT_RAW | The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. |
| OUT_EOF_CH1_INT_RAW | The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. |
| OUT_DSCR_ERR_CH1_INT_RAW | The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. |
| OUT_TOTAL_EOF_CH1_INT_RAW | The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. |
| OUTFIFO_OVF_L1_CH1_INT_RAW | The raw interrupt bit turns to high level when fifo is overflow. |
| OUTFIFO_UDF_L1_CH1_INT_RAW | The raw interrupt bit turns to high level when fifo is underflow. |
| OUTFIFO_OVF_L2_CH1_INT_RAW | The raw interrupt bit turns to high level when fifo is overflow. |
| OUTFIFO_UDF_L2_CH1_INT_RAW | The raw interrupt bit turns to high level when fifo is underflow. |
| OUT_DSCR_TASK_OVF_CH1_INT_RAW | The raw interrupt bit turns to high level when dscr ready task fifo is overflow. |